1. Field of the Invention
The present invention relates to a thin film transistor, a fabrication method thereof and a liquid crystal display having the thin film transistor.
2. Description of the Related Art
One of the switching elements used in an active matrix type liquid crystal display is a thin film transistor (TFT). A structure of the thin film transistor is divided roughly into the so-called bottom-gate-type inverted staggered structure in which a gate electrode is formed on a glass substrate side rather than source and drain electrodes side and the so-called top-gate-type staggered structure or planer-type structure in which the source and the drain electrodes are formed on a glass substrate side rather than a gate electrode. Among these, a bottom-gate-type thin film transistor can be further divided into two structures. One is a structure in which a channel protection film is formed on an operational semiconductor film forming a channel portion and the other is a structure in which a portion of an upper layer of the operational semiconductor film is etched without having the channel protection film.
A cross sectional structure of the conventional bottom-gate-type thin film transistor having the channel protection film is described with reference to FIG. 21. A thin film transistor 100 has a bottom-gate-type gate electrode 104 formed on a glass substrate 102. A gate insulating film 106 made of SiNx (silicon nitride) is formed on the gate electrode 104 and the glass substrate 100. An operational semiconductor layer 108 made of, for example, amorphous silicon (a-Si:H; hereinafter, simply referred to as a-Si) is formed on the gate insulating film 106, and a channel protection film 110 made of SiNx is formed on the operational semiconductor layer 108 on the gate electrode 104. An impurity semiconductor layer (ohmic semiconductor layer) 112 and source and drain electrodes 114 and 115 are formed running over opposing edge portions of the channel protection film 110. The deposit from the gate insulating film 106 to the channel protection film 110 are sequentially formed by a plasma CVD method (PCVD method). An interlayer insulating film 116 is formed on the source electrode and the drain electrode 115 and on the channel protection film 110 exposed between the opposing edge portions of the source electrode 114 and the drain electrode and 115. A contact hole is formed on the interlayer insulating film 116 on the source electrode 114 and a pixel electrode 118 formed on the interlayer insulating film 116 is connected with the source electrode 114.
When forming the channel protection film 110 by patterning an inorganic insulating film, a back exposure is performed from the back side of the glass substrate 102 (lower part of FIG. 21). Thus, the channel protection film 110 is self-aligningly formed by using the gate electrode 104 as a mask.
When patterning the source electrode 114 and the drain electrode 115 from a metal layer formed on a whole surface, the source electrode 114 and the drain electrode 115 on the channel protection film 110 are separated taking a mask pattern positioning error in the photolithography process into consideration. Therefore, the source electrode 114 and the drain electrode 115 are structured so that the edge portions thereof respectively have overlapping areas shown by ΔL in the diagram with respect to the gate electrode 104 and face each other by running over the edge portions of the channel protection film 110.
Next, an operational theory of the thin film transistor is briefly described. For example, in the case of a n-type thin film transistor having a n+-type ohmic semiconductor layer 112, a channel area of the operational semiconductor layer 108 is in an “ON” state with a low resistance when a voltage with a positive polarity is applied to the gate electrode 104, and the channel area is in an “OFF” state with a high resistance when a voltage with a negative polarity is applied to the gate electrode 104.
On the other hand, in the case of a p-type thin film transistor having a p+-type ohmic semiconductor layer 112, the channel area is in an “ON” state with a low resistance when a voltage with a negative polarity is applied to the gate electrode 104, and the channel area is in an “OFF” state with a high resistance when a voltage with a positive polarity is applied to the gate electrode 104. Thus, a conduction (“ON”) state and cutoff (“OFF”) state of a thin film transistor can be controlled by applying a predetermined voltage to the gate electrode 104.
By the way, since the source electrode 114 and the drain electrode 115 overlap (overlapping length: ΔL) on the channel area (or the gate electrode area) in the conventional bottom-gate-type thin film transistor in which the channel protection film 110 is formed as described above, capacitances are formed between the source 114 and the drain electrode 115, the channel protection film 110, and the operational semiconductor film 108, thereby generating undesirable parasitic capacitances (Cp=(∈0∈s/ts)×W×ΔL). The parasitic capacitances Cp are in proportion to the inverse number of the overlapping length ΔL, overlapping width W, a relative dielectric constant ∈s of the channel protection film 110, and a film thickness ts of the channel protection film 110. It will be noted that ∈0  is a vacuum dielectric constant.
An active matrix type liquid crystal display using this thin film transistor as a switching element has a problem in which a pixel effective voltage is reduced due to a field-through voltage resulted from the parasitic capacitances Cp, thereby generating a degradation of picture quality such as flickering of the display, a reduction in contrast and the like.
In the separation process of the source electrode 114 and the drain electrode 115 by patterning a metal layer on the channel protection film 110, a slit is formed on the channel protection film (SiNx film) 10 by using an RIE (reactive ion etching). Therefore, permanent damages such as a trap level in a film and the like due to ion bombardment are generated to an SiNx film of the channel protection film 110, and a possibility of a reduction in electric characteristics or a long-term reliability of the thin film transistor exists, thereby resulting in an obstacle for improving a fabrication yield.